PLLs are used to accurately obtain various frequencies needed in systems. PLLS are necessarily mounted on general digital large-scale integration (LSI) circuits, such as a central processing unit (CPU) processor, a microcomputer, a digital system-on-chip (SoC), a baseband-processor, and a field programmable gate array (FPGA). The uses of PLLs include keeping generating a constant frequency as in the case of the clock of a microcomputer, and frequently changing frequencies as in the case of wireless communication.
Conventionally, PLLs have been able to substantially meet required specifications only by stably being operated. It has been sufficed that PLLs can obtain high-precision output with less frequency variation and less error. However, in recent years, there has been increased a demand for high-speed response, in addition to a demand for appropriate spectrum purity, i.e., less spurious-signal and less phase noise. More specifically, in digital communication/broadcast, high-speed frequency switching PLLs are required. In the case of the use of frequently switching frequencies, a response characteristic on the time axis, which is difficult to perceive from a frequency characteristic, becomes problematic.
In addition, in order to reduce the electric-power consumption of LSIs, a normally-off type computer has been proposed. In the normally-off type computer, electric-power supplied to each circuit is frequently interrupted. When electric-power is interrupted, a PLL loses a stable operation state. When the PLL is powered again, a time-delay at least in the order of several milliseconds (ms) is caused until an operation of the PLL is stabilized. Although it can be considered to exclude the PLL from targets of the interruption of the supply of electric-power thereto, the consumption electric-current of the PLL is in the order of 10 milliamperes (mA). Thus, if the PLL is excluded from targets of the interruption of the supply of electric-power, the power consumption thereof cannot sufficiently be reduced. If the PLL is designed by placing importance only on the speed-up of the PLL, an output frequency thereof is unstable. Thus, it is difficult to apply the PLL in applications. Consequently, a PLL with stability and fast response capability has been desired.